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Contents.Technical design Contemporary field-programmable gate arrays (FPGAs) have large resources of and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/O rates and bidirectional data, it becomes a challenge to verify correct timing of valid data within setup time and hold time.enables resource allocation within FPGAs to meet these time constraints. FPGAs can be used to implement any logical function that an can perform. The ability to update the functionality after shipping, of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise or unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.

Also common are quartz-, on-chip resistance-capacitance oscillators, and with embedded used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential on input pins designed to be connected to channels. A few ' FPGAs' have integrated peripheral (ADCs) and (DACs) with analog signal conditioning blocks allowing them to operate as a (SoC). Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and (FPAA), which carries analog values on its internal programmable interconnect fabric.History The FPGA industry sprouted from (PROM) and (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the die to erase the cells that held the device configuration.

In December 2015, acquired Altera.co-founders and invented the first commercially viable field-programmable in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. The XC2064 had 64 configurable logic blocks (CLBs), with two three-input (LUTs).

More than 20 years later, Freeman was entered into the for his invention.In 1987, the funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market share. By 1993, Actel (now ) was serving about 18 percent of the market.

By 2013, Altera (31 percent), Actel (10 percent) and Xilinx (36 percent) together represented approximately 77 percent of the FPGA market.The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the that operate their ), due to the advantage FPGAs deliver.

Microsoft began using FPGAs to Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their platform. Integration. This section needs additional citations for. Unsourced material may be challenged and removed.Find sources: – ( June 2017) In 2012 the coarse-grained architectural approach was taken a step further by combining the and interconnects of traditional FPGAs with embedded and related peripherals to form a complete '.

This work mirrors the architecture created by Ron Perloff and Hanan Potash of Burroughs Advanced Systems Group in 1982 which combined a reconfigurable on a single chip called the SB24.Examples of such hybrid technologies can be found in the Zynq-7000 all, which includes a 1.0 dual-core MPCore processor within the FPGA's logic fabric or in the Arria V FPGA, which includes an 800 MHz MPCore. The FPSLIC is another such device, which uses an processor in combination with Atmel's programmable logic architecture. The devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of and 64 kB of RAM) and analog such as a multi-channel and to their -based FPGA fabric. A Zynq-7000 All Programmable System on a Chip. Soft Core An alternate approach to using hard-macro processors is to make use of that are implemented within the FPGA logic., and are examples of popular. Many modern FPGAs are programmed at 'run time', which has led to the idea of or reconfigurable systems – that reconfigure themselves to suit the task at hand.

Additionally, new, non-FPGA architectures are beginning to emerge. This article needs to be updated. In particular: It relies on a report from February 2009, nearly 10 years ago; in which many changes have occurred. Please update this section to reflect recent events or newly available information. ( December 2018)Xilinx claimed that several market and technology dynamics are changing the ASIC/FPGA paradigm as of February 2009:.

development costs were rising aggressively. ASIC complexity has lengthened development time. resources and headcount were decreasing.

Revenue losses for slow time-to-market were increasing. Financial constraints in a poor economy were driving low-cost technologies. These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts (see ).Some FPGAs have the capability of that lets one portion of the device be re-programmed while other portions continue running. Complex Programmable Logic Devices (CPLD) The primary differences between (CPLDs) and FPGAs are. A CPLD has a comparatively restrictive structure consisting of one or more programmable logic arrays feeding a relatively small number of clocked. As a result, CPLDs are less flexible, but have the advantage of more predictable and a higher logic-to-interconnect ratio.

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FPGA architectures, on the other hand, are dominated. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex (EDA) software.In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex such as,. Another common distinction is that CPLDs contain embedded to store their configuration while FPGAs usually require external (but not always).When a design requires simple instant-on CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design.

In those designs, CPLDs generally perform glue logic functions, and are responsible for “” the FPGA as well as controlling and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design. Security considerations FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning. FPGAs' flexibility makes malicious modifications during a lower risk. Previously, for many FPGAs, the design was exposed while the FPGA loads it from external memory (typically on every power-on). All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream. For example, and offer encryption (up to 256-bit) for bitstreams stored in an external flash memory.FPGAs that store their configuration internally in nonvolatile flash memory, such as 's ProAsic 3 or 's XP2 programmable devices, do not expose the bitstream and do not need.

In addition, flash memory for a provides protection for space applications. Customers wanting a higher guarantee of tamper resistance can use write-once, FPGAs from vendors such as.With its Stratix 10 FPGAs and SoCs, introduced a Secure Device Manager and physically uncloneable functions to provide high levels of protection against physical attacks.In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that FPGAs can be vulnerable to hostile intent. They discovered a critical had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and, accessing unencrypted bitstream, modifying silicon features, and extracting data. Applications. See also:An FPGA can be used to solve any problem which is. This is trivially proven by the fact that FPGAs can be used to implement a, such as the Xilinx or Altera.

Their advantage lies in that they are significantly faster for some applications because of their and in terms of the number of gates used for certain processes.FPGAs originally began as competitors to to implement for. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full (SoCs). Particularly with the introduction of dedicated into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of (DSPs) began to incorporate FPGAs instead.Another trend in the use of FPGAs is, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a generic processor. The search engine is noted for adopting FPGA acceleration for its search algorithm in 2014.

As of 2018, FPGAs are seeing increased use as including Microsoft's so-termed 'Project Catapult' and for accelerating for applications.TraditionallyFPGAs have been reserved for specific where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. As of 2017, new cost and performance dynamics have broadened the range of viable applications.Common applications.

Aerospace and Defense. Avionics/. Communications. Missiles & Munitions. Secure Solutions. Space (i.e.

Simplified example illustration of a logic cell (LUT –, FA –, DFF – )The most common FPGA architecture consists of an array of, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array.An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic.For example, a requires much more routing than a with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of (LUTs) and I/Os can be. This is determined by estimates such as those derived from or by experiments with existing designs.

As of 2018, architectures for routing and interconnection are being developed.In general, a logic block consists of a few logical cells (called ALM, LE, slice etc.). A typical cell consists of a 4-input LUT , a (FA) and a, as shown above. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left (mux). In arithmetic mode, their outputs are fed to the adder.

The selection of mode is programmed into the middle MUX. The output can be either or, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the adder are into the LUTs in order to save. Hard blocks Modern FPGA families expand upon the above capabilities to include higher level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased speed compared to building them from logical primitives. Examples of these include, generic, high speed I/O logic and embedded.Higher-end FPGAs can contain high speed and hard IP cores such as, / controllers, and external memory controllers. These cores exist alongside the programmable fabric, but they are built out of instead of LUTs so they have ASIC-level and without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic.

The multi-gigabit transceivers also contain high performance analog input and output circuitry along with high-speed serializers and deserializers, components which cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.Clocking Most of the circuitry built inside of an FPGA is synchronous circuitry that requires a clock signal. FPGAs contain dedicated global and regional routing networks for clock and reset so they can be delivered with minimal. Also, FPGAs generally contain analog and/or components to synthesize new as well as attenuate. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate. These clock signals can be generated locally by an oscillator or they can be recovered from a high speed serial data stream.

Care must be taken when building circuitry to avoid. FPGAs generally contain block RAMs that are capable of working as with different clocks, aiding in the construction of building and dual port buffers that connect differing clock domains.3D architectures To shrink the size and power consumption of FPGAs, vendors such as and have introduced. Following the introduction of its 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.Xilinx's approach stacks several (three or four) active FPGA dies side-by-side on a silicon – a single piece of silicon that carries passive interconnect. The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a FPGA.Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other die/technologies to the FPGA using Intel's embedded multi-die interconnect bridge (EMIB) technology. Design and programming. Further information:, andTo define the behavior of the FPGA, the user provides a design in a (HDL) or as a design.

The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its component.Using an tool, a technology-mapped is generated. The netlist can then be fit to the actual FPGA architecture using a process called, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via, and other methodologies. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA.

This file is transferred to the FPGA/CPLD via a or to an external memory device like an.The most common HDLs are and as well as extensions such as. However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of, there are moves to raise the through the introduction of. ' graphical programming language (sometimes referred to as 'G') has an FPGA add-in module available to target and program FPGA hardware.To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called, and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as (typically released under licenses such as the, or similar license), and other sources. Such designs are known as '.'

In a typical, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the description in or is simulated by creating to simulate the system and observe results.

Then, after the engine has mapped the design to a netlist, the netlist is translated to a description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point can be added and the simulation run again with these values onto the netlist.More recently, (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in the C programming language and target FPGA functions as OpenCL kernels using OpenCL constructs. For further information, see and.Basic process technology types. – based on static memory technology.

In-system programmable and re-programmable. Requires external boot devices. Currently in use.

Notably, or devices may often load contents into internal SRAM that controls routing and logic. – One-time programmable. Obsolete. – One-time programmable.

CMOS. – Programmable Read-Only Memory technology.

One-time programmable because of plastic packaging. Obsolete. – Erasable Programmable Read-Only Memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. Obsolete.

– Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages.

Some but not all EEPROM devices can be in-system programmed. CMOS. – Flash-erase EPROM technology. Can be erased, even in plastic packages.

Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture.

CMOS.Major manufacturers In 2016, long-time industry rivals and (now an Intel ) were the FPGA market leaders.